Real World FPGA Design with Verilog
By: Ken Coffman, President of Bytech Services
Published by: Prentice Hall Professional Technical Reference, 2000
ISBN: 0-13-099851-6
Textbook (hard) cover, 291 pages
Includes CD-ROM
Price: $89.00 plus shipping
On request, this book can be autographed by the author.
Quantity
Real World FPGA Design with Verilog for $ 89.00 each
This book presents a practical and down-to-earth introduction to modern FPGA design practices with Verilog as the design capture method.
Chapter List
Foreword, Notes on the Current State of the Art, by Janick Bergeron
Preface, Digital Design in the Real World
Chapter 1, Verilog Design in the Real World
Chapter 2, Digital Design Strategies and Techniques
Chapter 3, A Digital Circuit Toolbox
Chapter 4, More Digital Circuits: Counters, RAMs, and FIFOs
Chapter 5, Verilog Test Fixtures
Chapter 6, Real World Design, Tools, Techniques, and Trade-offs
Chapter 7, A Look at Competing Architectures
Chapter 8, Libraries, Reusable Modules, and IP
Chapter 9, Designing for ASIC Conversion
Afterword, A Look into the Future
Excerpt from Chapter 2, Digital Design Strategies and Techniques:
SYNCHRONOUS LOGIC RULES
Metastability
Literally, metastability means beyond-settled? Something other than steady? If a signal is metastable, it is not stable, it is neither 1 nor 0, or it oscillates and will eventually resolve to a 1 or 0, but we don't know which. As a digital designer, I hope this idea keeps you up late at night.
Metastability occurs when a clock edge is random with respect to a change of an asynchronous input signal. If the relation of the clock and signal is truly random, then it is inevitable that an input change will occur so close to a clock edge that the output is unpredictable. This problem manifests itself as a flipflop output that takes a long time to resolve, often much longer than the typical clock-to-Q output delay listed in the flipflop datasheet.
Figure 2-13 illustrates the metastability problem; if SIGNAL changes within the setup/hold window of the flipflop, the output is unknown for a period. How long is this period? It depends on the characteristics of the flipflop and its environment: how fast is the flipflop, how much gain does it have, and how much noise is present in the system. How big is this problem? It depends on how often the input changes and how wide the setup/hold window is compared to the clock period. We'll never get to zero metastability, but hopefully the statistical probability of metastability will be microscopic. I don't know about you, but if I can get the mean time between failures in my design to 100,000 years or so, that's good enough.
The closest we will get to a solution to the metastability problem is to use synchronous design techniques. This means a synchronizing clock is used to qualify, gate, or trigger a circuit. The time between clock edges is used to allow signals to propagate and settle. It's like a game; if you can get your signal to the next flipflop before the next clock setup time, then you win.
Setup and Hold Time
For the output of a flipflop to be predictable (not metastable), the inputs must meet the setup and hold time requirement of the flipflop.
* The setup time, often represented as Tsu, is the time period, BEFORE the edge of the synchronizing clock, when the input is required to be stable. If the setup time is violated, the output value is indeterminate.
* The hold time, often represented as Th, is the time period, AFTER the synchronizing clock edge, when the input is required to be stable. If the hold time is violated, again the output value is not guaranteed. The setup and hold requirement comes from the analog nature of the flipflop design. The flipflop uses feedback implemented with cross-coupled gates to hold a state. It takes time for the gates to achieve their stable state. In a perfect world, an edge-triggered flipflop would change states exactly synchronous with the clock edge. The clock edge would be infinitely fast, and the flipflop would change states instantaneously. Real World clocks have rise/fall times, and flipflops require stable inputs during the setup/hold time to achieve a stable output state.
The flipflop metastability problem will never go away as long as a signal has a random phase relation to the flipflop clock. However, IC manufacturers have made great progress in closing the metastability window (this window is the setup plus hold time window). By increasing the speed of the flipflop, we make the metastability window narrower and less of a problem. The fact is, most problems that designers blame on metastability is related to asynchronous design technique. Each FPGA input should drive one and exactly one flipflop. The output of this single flipflop can be used to drive another flipflop for added security or can be used to drive the rest of your synchronous system. When an asynchronous input drives multiple flipflops, and the input changes near the clock edge, some flipflop outputs will change and some will not. This is not a metastability problem; this is an asynchronous input problem!
Figure 2-14 illustrates this. The RC delays represent signal delays due to routing and load inside the FPGA. We want all three flipflop outputs to be the same, but, depending on the phase of the input signal, sometimes the outputs will not be the same. If we synchronize the input with a single flipflop and do not violate its setup/hold time requirement, then all outputs are assured to be the same. That's what we want!
How can we absolutely assure that the inputs are not going to change during the setup and hold period of the flipflop? The answer is an important part of the solution for the question: "How can I create a nearly trouble-free design?"
Always synchronize your inputs! This means an asynchronous input drives exactly one flipflop. The output of this flipflop can be safely used to drive the rest of your synchronous circuitry.
