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	FREEBIE! On January 12, 1999, Ken Coffman gave a presentation for 35 people at the Computer Literacy bookstore in San Jose, California. The name of this presentation was Synchronicity in FPGA Designs, but other topics were also discussed. If you want a free copy of the slides used for this presentation, send your email request and snail-mail address using  this e-mail link. Return to top of page
	Bidirectional Bus Code // Bidirectional bus. // Ken Coffman, Bytech Services Jan 2000 module bus (CLK, RESET, OE1, OE2, DATA_IN1, DATA_IN2, DATA, Data_reg);     input CLK, RESET, OE1, OE2;     input [7 : 0] DATA_IN1, DATA_IN2;     inout [7 : 0] DATA;     output [7 : 0] Data_reg;     reg [7 : 0] Data_reg;     reg [7 : 0] DATA_BUS; // Bus input section (signals from outside world into FPGA).   always @ (posedge CLK or negedge RESET)   begin     if(~RESET)      Data_reg <= 8'b0;     else       Data_reg <= DATA;    end // Tristate output bus assignment. The designer must make sure // that OE1 or OE2 are not asserted at the same time. Also, // the designer must assure that the external bus driver is // not enabled when OE1 or OE2 are asserted. assign DATA = (OE1 | OE2) ? DATA_BUS : 8'bz; // Bus output section. This intentionally creates latches. // These signals will drive the outside world from the FPGA. always @ (DATA_IN1 or DATA_IN2 or OE1 or OE2)         begin case     ({OE2, OE1})     {1'b0, 1'b1}:       DATA_BUS = DATA_IN1;     {1'b1, 1'b0}:       DATA_BUS = DATA_IN2;     endcase     end     endmodule Return to top of page
	Reviews of "Real World FPGA Design with Verilog "Firstly, I'd like to thank you for a marvelously entertaining and highly readible book. As a Verilog newbie, I found it an excellent introduction; as a 28-year design veteran, I found it highly pragmatic; and as an author of a dozen articles, I'm envious that your editors were such good sports to let you get away with such colorful language!" Stephen L. Wasson Director of Reconfigurable Logic, MorphICs Technology * * * * * * I have to say, I like the book. The informal style is a real relief when reading a technical subject. It seems to be at about the right level of detail for me, and I like the quotes." George Stults Engineer, Advanced Technology Video * * * * * *"I have read through the whole book in the past few days. I have almost 5 years FPGA design experience with Nortel Network and Lucent Technologies. Through reading this book, there are many interesting sections [which] enhance my design knowledge. This book covered a lot of fields such as how to use the design tools, how the statistic timing analysis [works], coding styles etc. I think it is a nice book for all FPGA designers." Robert Xue Lucent Technologies * * * * * * "Thank you for sending me a copy of your book -- it looks great! At last, I have a book to recommend to budding FPGA designers which contains a recent copy of Silos!!" Richard O. Jones VP Sales, Simucad, Inc. * * * * * * "I read your book over the holidays. I enjoyed it a great deal. I found the chapter on Tools, Techniques, and Tradeoffs to be especially helpful (we use the Xilinx tools over here). It was nice reading! Thanks!" Ted Obuchowicz VLSI Engineer/CAD Specialist Dept. of Electrical and Computer Engineering Concordia University * * * * * * "Very nice, indeed. Thank you!  I'll give you credit in the book [Newton's Telecom Dictionary].  As a matter of fact, I'll mention your book and recommend it." Ray Horak, President and GPB The Context Corporation Author of Communications Systems & Networks and Senior Editor of Newton's Telecom Dictionary * * * * * * Return to top of page Oops! I goofed! Here is a list of known errors in "Real World FPGA Design with Verilog"
	Page 6 - In Listing 1-4, the last "always" should be bold. Error detected by Stephen Wasson. Page 9 - In Listing 1-5, "assign out" should read "assign out1". Also, near the end of Listing 1-5, delete bidir_signal from the fragment that reads "<= (in3 & bidir_signal);" so that it reads "<= (in3);" Errors detected by Stephen Wasson. Page 13 - In Listing 1-9, the line that reads "user_and u2 (test_out2, test_in2,), (test_in3));" should read "user_and u2 (test_out2, test_in2, test_in3);" Error detected by Stephen Wasson. Page 15 - In Tables 1-5 and 1-6, all upper case "X" should be lower case "x". Error detected by Stephen Wasson. Page 17 - In Table 1-12, all references to "Data" should be "data". In Tables 1-10, 1-11, and 1-12, any cell where data = x, or data = z, or control = x, or control = z should have an "x" output. Errors detected by Stephen Wasson. Page 20 - Figure 1-4 caption should say "Bipolar Transistor" instead of "CMOS". Error detected by Dave Graf. Page 21 - In Figure 1-5, change the caption from "Schematic of a Typical CMOS D Flipflop Implementation (Gates)" to "Schematic of a Typical CMOS D Flipflop Implementation (Gates) Note: PRESET and CLEAR inputs are active low signals". Error detected by Stephen Wasson. Pages 23 and 24 - The titles for the Listings 1-13 and 1-14 are wrong.  Listing 1-13 should be titled: "Cascaded Flipflops with Asynchronous Reset" and Listing 1-14 should be titled: "Verilog Flipflop with Synchronous Reset".   The title for Figure 1-8 should be: "Schematic for Cascaded Flipflops with Asynchronous Reset". Also the text of page 24 should be changed to reflect the new listing titles. The above errors were detected by Robert Xue of Lucent Technologies. Page 24 - the register list in Listing 1-14 should include "test_out1, test_out2;" not "test_out1, test_out1;" Error detected by Ted Obuchowicz of Concordia University. Page 27 - In Listing 1-16, in the top comment, the sentence fragment "One set of flipflops is created..." should read "One flipflop is created...". Error detected by Stephen Wasson. Page 28 - In the last line of the middle paragraph, "Listing 1-15" should be "Listing 1-16". Error detected by Stephen Wasson. Page 29 - The caption for Figure 1-12 "Nonblocking Assignment Example 3" should be "Nonblocking Assignment Example". Error detected by Stephen Wasson. Page 30 - In Listing 1-18, insert the line "output c, d, e;" between the "input...." and "reg [3:0]..." lines. Align tabs. Error detected by Stephen Wasson. Page 31 - In Listing 1-18, the "end" before the "else begin" line should be bold. In Listing 1-19 the fragment "// b = 1'b0." should read "// b = 1'b1.". In Listing 1-21, add the line "output a, b, c, d, e, g;" just before the line that reads "reg a;". Also in Listing 1-21 change the "module and_or (clk, resetn, and_test, or_test);" to "module and_or (clk, resetn, and_test, or_test, a, b, c, d, e, g);" Errors detected by Stephen Wasson. Page 32 - In Listing 1-21, the fragment that reads "...d gets assigned value of 0." should read "...d gets assigned value of 1.". The fragment on the next line that reads "...e gets assigned the value of 1010." should read "...e gets assigned the value of 0001". The fragment that reads "...e gets assigned value of all 1's (1111)." should read "...e gets assigned the value of 0101.". Errors detected by Stephen Wasson. Page 33 - In Listing 1-22, the line "input clk, resetn, and_test, or_test;" should read "input clk, resetn;" and the line "g <= 4'b01001;" should be "g <= 5'b01001;". Also in Listing 1-22, after the line that reads "input clk, resetn;", insert the line: "output b, c, d, e, g, h, i, j;" and line up tabs. Also in Listing 1-22, change the first line from module "eq_test (clk, resetn, and_test, or_test);" to "module eq_test (clk, resetn, and_test, or_test, b, c, d, e, g, h, i, j); Errors detected by Stephen Wasson. Page 34 - In Listing 1-22, near the bottom of the page, change the fragment "...e == !i..." to "...e == ~i". Error detected by Stephen Wasson. Page 35 - In the Shift Operators section, change the sentence "Operating on a value which contains an x or a z gives an x result in all bit positions" to "Shifting a value which contains an x or a z will propagate the x or z in the direction of the shift.". In Listing 1-23, after the "input shift_left_test;" line insert the line: "output a, b, c, d, e, f;" and align the tabs. Change the first line of Listing 1-23 from "module shifter (clk, resetn, shift_right_test, shift_left_test);" to "module shifter (clk, resetn, shift_right_test, shift_left_test, a, b, c, d, e, f);" Errors detected by Stephen Wasson. Page 36 - In Listing 1-23, about one-third of the way down the page, the fragment that reads "// Result is xxxx because of the x in e." should read "// Result is 0x00 because of the x in e." Also in Listing 1-23, about two-thirds of the way down the page, the fragment that reads "// Result is xxxx because of the x in e." should read "// Result is 0000." Errors detected by Stephen Wasson. Page 43 - In Figure 2-1, the transistors labeled N FET and P FET are reversed. Error detected by Stephen Wasson. Page 47 - The schematic of Figure 2-5 does not match the design of Listing 2-1 (the schematic was not updated when an additional stage of flipflops were inserted in the code). Also, the schematic does not show the missing overheat_out hold logic (feedback). Errors detected by Stephen Wasson. Page 51 - In the last paragraph, the fragment "c[1] (ix51)" should be "c[0] (ix72)" and the fragment "c[0] (ix50)" should be "c[1] (ix71)". Error detected by Stephen Wasson. Page 55 - In the first line the fragment "...where the simple OR gate might be used..." should be "...where the simple NOR gate might be used...". Error detected by Stephen Wasson. Page 63 - In the fifth paragraph, the sentence that reads "--or worse, we'll violate the setup time of U2..." should read "--or worse, we'll violate the setup or hold time (depending how much delay occurs) of U2..." Error detected by Robert Xue of Lucent Technologies. Page 64 - In the Using Alternate Clock Edges section, change the sentence that reads "Careful analysis must be done to assure that the timing works out." to "Careful analysis must be done to assure that the timing works out, including accounting for clocks that do not have a 50% duty cycle." Added information suggested by Stephen Wasson. Page 67 - In the first paragraph, the sentence that starts with "This means that code like Listing 2-9,..." should be "This means that code like Listing 2-10,...". Error detected by Stephen Wasson. Page 70 - The last sentence refers to Listing 2-10, it should refer to Listing 2-11. Error detected by Robert Xue of Lucent Technologies. Page 78 - On the top of the page, the sentence that reads "Listing 3-1 contains some example file names." should read "Listing 3-1 contains some example signal names.". The last sentence on this page that reads "Internal tristates can cause also..." should read "Internal tristates can also cause...". Errors detected by Stephen Wasson. Page 84 - In Figure 3-4, the schematic is incorrect; the direction_sig connection is not shown. Error detected by Stephen Wasson. Page 85 - In the first line of the first paragraph, add a comma so the fragment that reads "and selected or all input..." reads "and selected, or all input...". Error detected by Stephen Wasson. Page 89 - In Listing 3-8, add "or m" (with the m in bold) in four places so lines that read "always @ (e or f or g or h or i or j or k or l)" read "always @ (e or f or g or h or i or j or k or l or m)". Errors detected by Stephen Wasson. Page 91 - In the first sentence of the paragraph that follows Figure 3-15, the fragment that reads "..., four layers of logic compared to five." should read "..., two layers of logic compared to three.". Error detected by Stephen Wasson. Page 93 - Near the botton of the page, the fragment that reads "...uses 16 packed CLBs..." should read "...uses 16 partially-used CLBs..." Error detected by Stephen Wasson. Page 95 - In Listing 3-11, the line that reads "lower_level u1..." should read "lower_lev u1...". Error detected by Stephen Wasson. Page 96 - In the first line of the paragraph that follows Figure 3-19, the fragment that reads "..., a MUX can used..." should be "..., a MUX can be used..." Error detected by Stephen Wasson. Page 100 - The schematic of Figure 3-20 is erroneous, the "flag_output" and asynchronous "reset" signals are missing. Errors detected by Stephen Wasson. Page 102 - The caption for Listing 3-16 should say "Verilog Code for Converting Gray Code to Binary" instead of "Binary to Gray Code". Error detected by Jaime Villela of Fujitsu Network Communications. Page 106 - The heading in Figure 3-22 should be: "sum output" Error detected by Ted Obuchowicz of Concordia University. Page 109 - The schematic of Figure 3-26 is erroneous, the reg_carry_out signal to the DFFRS flipflop is missing. Error detected by Stephen Wasson. Page 113 - The word "call" in the middle of the page (in the sentence that begins "Oddly enough") should be the word "called". Error detected by Jaime Villela of Fujitsu Network Communications. Page 114 - In the first line of the second paragraph in the Carry Skip Adder section, the fragment that reads "...which area for speed." should read "...which trades area for speed." The next-to-last sentence of the Subtractors section reads "We will discuss the Ripple Borrow Adder to illustrate the similarity to Adder circuits." should read "The logic for the Ripple Borrow Subtractor is shown in Listing 3-29 to illustrate the similarity to Adder circuits.". Error detected by Stephen Wasson. Page 116 - In the last paragraph of the Multipliers section, change the sentence fragment "The result of multiplication..." to "The result of unsigned multiplication...". Clarification submitted by Stephen Wasson. Page 116 - In the second sentence, the phrase "This in not a big..." should be "This is not a big..." Error detected by Ted Obuchowicz of Concordia University. Page 118 - In the next-to-last line of Listing 3-31, reduce the font size of the "end" to match the font size of "endmodule". Error detected by Stephen Wasson. Page 119 - Change the first part of the first sentence from "To multiply a nibble by 0.75, realize that 0.75 X 4 = 2..." to "To multiply a nibble by 0.75, realize that 0.75 X 4 = 3..." Error detected by Stephen Wasson. Page 122 - About three-quarters into the first paragraph of the Johnson Counters section, the fragment that reads "..., where n is the number of registers)... should be "..., where n is the maximum count value)..." Error detected by Stephen Wasson. Page 125 - Near the top of the page, the fragment that reads "can create counts of up to 2n-1..." (where 'n-1' is superscript) should read can create counts of up to 2n-1" where only the 'n' is superscript. In the first sentence of the last paragraph, the fragment that reads "I use this generally..." should read "I generally...". Errors detected by Stephen Wasson. Page 127 - In the second sentence, "LSFR" should be "LFSR". Error detected by Ted Obuchowicz of Concordia University. Page 128 - In the caption of Listing 4-7 the fragment that reads "Verilog Version of a 8-bit..." should be "Verilog Version of an 8-bit..." Error detected by Stephen Wasson. Page 133 - Near the bottom of the page, the sentence fragment that reads "...which implements a LFSR." should be "...which implements an LFSR." Error detected by Stephen Wasson. Page 134 - In the schematic of Figure 4-8, the clock line should be extended to connect to all the registers. In Listing 4-11, the line "crc_output[0] <= crc_output[15] ^ serial_data_out;" should be "crc_output[0] <= serial_data_out;". Errors detected by Stephen Wasson. Page 136 - In the end of the first sentence, the fragment "...whereas our earlier design used 1 packed CLB)." should read "...whereas our earlier design used a single 2LUT)." Error detected by Stephen Wasson. Page 137 - In the first line of the first paragraph, the fragment that reads "= 16 address lines or ..." should read "= 16 addresses or ...". The caption for Listing 4-13 is "Listing 4-13 Verilog 16x1 RAM Example using CLBs" should say "Listing 4-13 Verilog 16x1 RAM Example using CLB Flipflops" Errors detected by Stephen Wasson. Page 137 - In Listing 4-13, the line that includes "? ram_data_reg[ram_data_reg[ram_addr]]" should be "? ram_data_reg[ram_addr]" Error detected by Ted Obuchowicz of Concordia University. Page 139 - The caption for Figure 4-10 is "Figure 4-10 Schematic for Verilog 16x1 RAM Example using CLBs" should say "Figure 4-10 Schematic for Verilog 16x1 RAM Example using CLB Flipflops" Error detected by Stephen Wasson. Page 140 - In the first sentence, the fragment "...RAM with FPGA CLBs." should read "...RAM with CLB flipflops." Error detected by Stephen Wasson. Page 157 - In the last line of the first paragraph, the $write should be bold. Error detected by Stephen Wasson. Page 167 - In the middle of the second paragraph, the fragment that reads "...pyramidal filter uses five..." should read "...pyramidal filter that uses five...". Error detected by Stephen Wasson. Page 188 - The sentence fragment in the second sentence "...our logic to 2- and 4-input..." should be "...our logic to 2-, 3-, and 4-input...". Clarification provided by Stephen Wasson. Page 201 - The sentence fragment in the second-to-last sentence "The mapper output is an .ncf (physical netlist format) file." should be "The mapper output is map.ncd.". Error detected by Stephen Wasson. Page 202 - In the Pack CLB Registers for Minimum Area or Structure section, in the first sentence, the fragment that reads "... ordering but analyzing bussed..." should read "... ordering by analyzing bussed...". Delete all text in the Generate 5-Input Functions section and insert the following sentence: "The Xilinx 3K family supports an optional 5-input LUT configuration." Errors detected by Stephen Wasson. Page 206 - In the Report Paths Using Advanced Design Analysis (No Timing Constraints) section, in the first sentence, the fragment that reads "..., or s number from..." should read "..., or a number from..." Error detected by Stephen Wasson. Page 210 - Replace all text in the Synchronize Start-up to Done Input Pin section with "Done is an open-drain signal that can be tied to multiple FPGAs. With the "Synchronize Done" mode enabled, all devices will hold off "starting" until the last device has been configured." Error detected by Stephen Wasson. Pages 212-214 - The section heading "Floor Planner" should be "Floorplanner". Make this same change in the captions of Figures 6-12 and 6-13. Errors detected by Stephen Wasson. Page 225 - In the second sentence of the second paragraph, change the fragment "...via serial EPROM..." to "...via serial PROM..." Error detected by Stephen Wasson. Page 229 - In Figure 7-6, the "G1" input should be labelled as "GX". Error detected by Stephen Wasson. Page 231 - In the first line of the first paragraph of the Altera FLEX8K Architecture section, change the fragment that reads "...is a SRAM-based..." to "...is an SRAM-based...". Error detected by Stephen Wasson. Page 250 - Near the end of the first paragraph, change "Figure 3-6" to "Figure 8-6". Error detected by Stephen Wasson. Page 255 - In the second line of the first paragraph, change the fragment that reads "..., with all other circuitry and routing forced around it." to "..., with all other logic and routing forced around and through it." Delete the last sentence. Errors detected by Stephen Wasson. Page 262 - In the Synchronous Design Rules section, about two-thirds of the way into the first paragraph, the fragment that reads "My personal preference is to run a design at the possible lowest speed,..." should read "My personal preference is to run a design at the lowest possible speed,...". Error detected by Stephen Wasson. Page 267 - In the first sentence of the Boundary Scan section, the fragment that reads "... devices can reprogrammed." should read "... devices can be reprogrammed." Error detected by Stephen Wasson. Page 277 - The Glossary entry for DRAM reads "Dynamic Read-Only Memory" and should be "Dynamic Random Access Memory". Error detected by Glade Bacon of Microsoft. Return to top of page Related Web Sites Janick Bergeron is a leading industry expert on all things related to design verification, SOC, reuse, and large digital designs. Surf over to his site for additional information. Writing Testbenches:Function Verification of HDL Models Return to top of page